Low power consumption has become one of the most important features of current electronic systems. For popular consumer electronic applications such as mobile smart phones and tablets, low power consumption may be the tightest constraint in the design. Consequently, various techniques and tools that enable tight power consumption control during design have been developed. Many of these techniques and tools rely on changing the architecture or the technology of the circuit. But once these architectural or technological improvements have been made, it is the switching of the logic that will affect the power consumption.
One cause of the switching activity is signal propagation delays. FIG. 1 illustrates an example about how the switching activity can be caused by gate delays. The circuit 100 shown in the figure has a NOT gate 110 and an AND gate 120. The signal waveforms at nodes A, B and C are shown below. As can be seen from the waveforms, due to the delay of switching from high to low by the output of the NOT gate 110, the AND gate 120 outputs an unwanted pulse. In addition to the gate delay, wires can also cause a propagation delay. Wires have an approximate propagation delay of 1 ns for every 6 inches (15 cm) of length, while logic gates can have propagation delays ranging from more than 10 ns down to the picosecond range, depending on the technology being used.
The switching activity can be propagated and accumulated in a circuit, causing high cumulative switching activity in a portion of a circuit. Each node in the portion of the circuit has a switching activity value. The sum of the switching activity values for all of the nodes gives rise to a cumulative switching activity value, which can be extremely high. FIG. 2 illustrates an XOR tree commonly used in arithmetic operations such as addition and multiplication. The XOR tree 200 is formed by a plurality of three-input XOR gates. For a three-input XOR gate, the output is 0 if the initial state of the input signal is 101. On a given clock edge, the input signal changes to 010 and then the output of the XOR gate should switch to 1. Suppose, however, signals for the three input ports of the XOR gate arrive at different times under a sequence of “101-111-011-010”. The output will go through a sequence of “0-1-0-1”. Two unwanted transitions are thus caused by the delay. The unwanted transitions and propagation delays can cause more unwanted transitions at the output ports of the downstream XOR gates. The more stages of the XOR tree, the more unwanted transitions. Thus, a big and deep XOR tree can have a cumulative switching activity value close to a million.
Retiming has been proposed in some research papers as a technique to minimize the switching activity caused by the propagation delay. The technique is based on the observation that the output of a circuit state element such as a flip flop and a latch has fewer transitions than the input of the circuit state element. In particular, unwanted transitions can be blocked. To determine where to reposition circuit state elements, those research papers discuss employing some models to estimate average switching activity. While reasonably accurate, these models require significant computing resources and may not be feasible for applications to current large circuit designs. More efficient techniques are desirable.